1. Field of the Invention
The present invention relates to a low-cost, efficient semiconductor device manufacturing method for connecting electrodes of a pair of bases (e.g., a pair of a semiconductor chip and a circuit board, or a pair of semiconductor chips) together in a short time.
2. Description of the Related Art
Electronic devices have become faster and smaller, and there is an increasing demand for high-density packaging of their electronic components.
Against this background, as a method for bonding a semiconductor component (semiconductor chip) on its substrate, so-called flip-chip bonding (face down bonding) has been employed in which one surface of the semiconductor chip is allowed to face the substrate, followed by bonding of electrodes on the chip to electrodes of the substrate
In this flip-chip bonding strategy, bump electrodes for external connection are formed on the electrode pads of the semiconductor chip, and these bump electrodes are connected to the electrode interconnections of the substrate mechanically and electrically.
FIG. 7A illustrates an example of a so-called BGA (Ball Grid Array) semiconductor device having a semiconductor chip mounted on a substrate by flip-chip bonding. Moreover, FIGS. 7B to 7I illustrate an example of a manufacturing method for the semiconductor device.
As shown in FIG. 7A, the BGA semiconductor device includes a semiconductor chip 1A that is flip-chip mounted on the surface of a substrate 7 (also referred to as an interposer, or a circuit board) and is sealed with mold resin 8, with bumps 1B on the electrode pads of the semiconductor chip 1A being connected to electrodes 7B of the substrate 7 mechanically and electrically.
On the backside (the other surface) of the substrate 7, solder balls 9 are arranged as connection terminals.
A BGA semiconductor device of this sort is manufactured in the following manner: A semiconductor substrate 1 with a plurality of semiconductor components (semiconductor chips), each having bumps on its electrode pads and being formed over one surface of the semiconductor substrate 1 through a given wafer process as shown in FIG. 7B, is attached to a dicing tape 3 attached to a WF ring (wafer ring) 2 as shown in FIG. 7C.
The semiconductor substrate 1 is then cut into individual semiconductor chips 1A by, for example, blade dicing using a dicing blade B and, as shown in FIG. 7D, the dicing tape 3 is expanded to separate the semiconductor chips 1A from one another.
Using push-up pins (not shown) the semiconductor chips 1A are pushed up under the dicing tape 3 to be separated from the dicing tape 3, causing an holding tool T1 held above the semiconductor chips 1A to pick them up, and the holding tool T1 transfer them on a chip tray 4 for storage.
As shown in FIG. 7E, a holding tool T2 is then operated to pick up one of the semiconductor chips 1A from the chip tray 4. Before picking up, a camera 5 arranged above the semiconductor chip 1A recognizes the position of the semiconductor chip 1A on the chip tray 4 for position correction to ensure precise positioning of the holding tool T2.
Subsequently, the holding tool T2 carrying the semiconductor chip 1A is inverted, allowing the semiconductor chip 1A to be transferred to another holding tool T3 arranged above.
As shown in FIG. 7F, while recognizing by a lower camera 6A the positions of the electrode pads of the semiconductor chip 1A held by the holding tool T3, the positions of electrodes of the substrate 7 on which the semiconductor chip 1A is to be mounted are recognized by an upper camera 6B. The X, Y, and θ positions of the holding tool T3 are then corrected on the basis of the recognition results from the cameras 6A and 6B for precise alignment of the electrodes.
As shown in FIG. 7G, the semiconductor chips 1A are then sequentially bonded to the substrate 7 which has previously been coated with a pasty or film-shaped underfiller 7A.
As shown in FIG. 7H, the semiconductor chips 1A on the substrate 7 are sealed with the mold resin 8 at a time.
Solder balls 9 that serve as connection terminals are arranged over the backside of the substrate 7.
Thereafter, as shown in FIG. 7I, the substrate 7 sealed with mold resin 8 is cut into individual pieces by blade dicing using a second dicing blade B, thereby providing a separate semiconductor device as shown in FIG. 7A.
In a case where the semiconductor device is formed through such a manufacturing process, prior to flip-chip bonding, the positions of electrodes of the semiconductor chip and the positions of electrodes of the substrate are recognized, and position correction is made on the basis of the obtained positional information. In addition, each step is carried out on a chip-by-chip basis, requiring a great amount of time and increasing the manufacturing costs.
Methods have been proposed in which electrodes of semiconductor chips are magnetically aligned with those of the substrate before connecting them together (see Japanese Patent Application Laid-Open (JP-A) No. 62-001257, 2002-057433, 11-266076, and 10-112477).
For example, JP-A No. 62-001257 discloses a method in which alignment is made using magnetic material embedded in through holes, and JP-A No. 2002-057433 discloses a method in which magnets are arranged over the chips so that magnetic material on the substrate and the chips attract each other for bonding of the chips to the substrate.
In addition, JP-A No. 11-266076 discloses a method in which print circuit board's electrodes having bumps made of magnetic material are magnetically aligned with substrate's electrodes having a magnetic layer for bonding, and JP-A No. 10-112477 discloses a method in which pieces of magnetic material of IC chips are magnetically aligned with magnetic layers of the circuit board for connecting their electrodes together.
These methods can realize easy alignment of electrodes by means of magnetic force, however, each step in the method is carried out on a chip-by-chip basis, resulting poor productivity.
Thus, low-cost, efficient semiconductor device manufacturing methods have not been provided yet, where electrodes of a pair of bases (e.g., a pair of a semiconductor chip and a circuit board, or a pair of semiconductor chips) are connected together in a short time, and therefore, a technology has been sought after that can achieve reduction in the manufacturing costs by high-speed processing.
It is an object of the present invention to solve the foregoing conventional problems and to achieve the object described below.
More specifically, it is an object of the present invention to provide a low-cost, efficient semiconductor device manufacturing method for connecting electrodes of a pair of bases (e.g., a pair of a semiconductor chip and a circuit board, or a pair of semiconductor chips) together in a short time.